TSMC has been flexing its 5nm process technology in recent weeks—first, with NXP and more recently with Cadence and Microsoft to cut down on semiconductor design timing signoff schedules.

Rendering of one of TSMC's 5nm production facilities

Rendering of one of TSMC’s 5nm production facilities. Image used courtesy of TSMC
 

In the NXP announcement, the company said they chose TSMC to help them develop an SoC platform in 5nm geared for next-gen automotive processors. What does the new 5nm process offer, and what will this mean for designers?

Reducing Silicon Size

While the first ICs only included a handful of transistors with features in the milimeter range, ICs now host billions of transistors with features in the single nanometer scale. Reducing the size of a transistor not only allows for more to fit onto a single chip but allows for more complex designs.

In the past, reducing transistor features was relatively easy to achieve by refining doping processes, improving optical equipment, and creating smaller masks. However, now that transistor feature sizes are in the nm range, the task becomes significantly more complex. With all these complexities, many semiconductor devices are reliant on highly complex processes that only a handful of fab houses are capable of meeting.

How Will NXP Use TSMC’s 5nm Process?

NXP has entered a collaboration with TSMC (Taiwan Semiconductor Manufacturing Company), to utilize TSMC’s 5nm Fin Field-Effect Transistor (FinFET) process technology. While this technology is usually optimized for mobile and high-performance computing applications, NXP plans to use it for automotive processors.

In recent years, NXP has invested development in the automotive and aerospace industries to create intelligent solutions for the future. Examples of applications from the upcoming NXP-TSMC collaboration will include connected cockpits, high-performance domain controllers, autonomous driving, networking, hybrid propulsion, and integrated chassis management.

5nm-based SoCs

The new 5nm-based SoCs will promote smart-connected technology in cars. Image used courtesy of NXP
 

TSMC’s new process technology called N5P is an enhanced version of its 5nm technology and has already caught the attention of multiple companies. In a TSMC blog post last year, Godfrey Cheng, TSMC’s head of global marketing, claimed that the new N5P will “feature the world’s highest transistor density and offer the fastest performance.”

The new N5P technology makes multiple improvements over its predecessor, the 7nm process. The first improvement is that it offers up to 20 percent faster speeds, enabling higher data rates. The second improvement is that it reduces power consumption by up to 40 percent, which allows for approximately twice the number of transistors for the same power consumption as previous devices.

Expanding a Unified Architecture

NXP plans to use the technology to expand its S32 architecture to create a system that allows for scalability and a common software environment.

NXP hopes that this will provide future automotive applications with a harmonized software infrastructure across domains so the underlying architecture is unified no matter the end application. The use of the 5nm process with its increased processing power allows for such an architecture.

NXP expects to see the first samples shipped to key customers in 2021.


The discussion on 5nm process technology and the new N5P often leads to discussions on Moore’s law. How have you seen opinions on Moore’s law vary throughout your career? Share your experiences in the comments below.

Source: All About Circuits