Since the 1960s, the IC industry has boomed, in part, because of powerful electronic design automation (EDA) tools. Two industry leaders, Cadence and Synopsys, were both developed in the mid-1980s and have remained industry staples for IC designers. Another EDA company Agnisys entered the market in the late 2000s and has since gained its share of popularity. 

In the past few months, these three major EDA companies have all introduced noteworthy improvements to their software suites. October has been a particularly busy month with news from both Cadence and Synopsys breaking only last week. In this article, we’ll cover each company’s updates and what they mean for practicing engineers.

Synopsys’ Silicon Lifestyle Management (SLM) Platform

Synopsys’ newest product, its Silicon Lifestyle Management (SLM) platform, intends to offer ongoing post-silicon analysis, maintenance, and optimization.

The company claims that this software tool is the industry’s first data-analytics-driven approach to optimizing SoCs. The platform is built to provide visibility into critical performance, reliability, and security issues for the entirety of a chip’s lifespan. In this way, Synopsys hopes to optimize operational activities at each stage of the device and system life cycles. 

Diagram of the Silicon Lifecycle Management (SLM) platform

Diagram of the Silicon Lifecycle Management (SLM) platform. Image used courtesy of Synopsys
 

The main idea of the new platform is that by applying targeted analytics engines that operate on available chip data, the tool can enable optimizations at each stage of the semiconductor lifecycle, from design implementation to manufacturing, production test, bring-up, and eventually in-field operation.

Cadence’s System VIP

Another newsworthy update to explore is Cadence’s release of its new software tool: System-Level Verification IP (VIP)

Cadence built VIP to offer new tools and libraries for automating SoC testbench assembly, bus and CPU traffic generation, cache-coherency validation, and system performance bottleneck analysis. 

Components of System VIP

Components of System VIP. Screenshot used courtesy of Cadence
 

The software has a built-in testbench generator, meant to allow engineers to test complex systems like memory and cache. This feature, coupled with the system traffic library, can help designers test factors such as coherency, performance, PCIE, and NVMe subsystems. 

Cadence claims that using this tool can help improve chip-level verification efficiency by up to ten times.

Agnisys’ SLIP-G and SoC Enterprise

In late July, Agnisys announced the release of three new products: SLIP-G, SoC Enterprise, and IDS NextGen (IDS-NG). We’ll briefly look at the two products most pertinent to IC design, SLIP-G and SoC Enterprise. 

The first new product, the Standard Library of IP Generators (SLIP-G), is meant to help SoC designers look for IPs in their design—whether the engineer should design them from scratch or pull IP off the shelf.

SLIP-G is a library of configurable IP generators that provides an interface for IP customization and configuration and generates the IP register-transfer-level (RTL) design, testbench models compliant with the universal verification methodology (UVM), and programming sequences. 

 Block diagram incorporating SLIP-G and SoC Enterprise

Block diagram incorporating SLIP-G and SoC Enterprise. Image used courtesy of Agnisys
 

Next, designers are tasked with assembling the SLIP-G IP and other blocks into an SoC. Agnisys’ next newly-released tool, SoC Enterprise (SoC-E), is an environment for design assembly.

SoC-E generates RTL aggregators, bridges, and multiplexors as needed by the SoC architecture. SoC-E works to automatically integrate and connect these blocks, SLIP-G IP, IP from other sources, and user blocks into a complete SoC.

The Usefulness of EDA Tools Depends on the Project

Each of these tools offers some significant improvements to software functionality to help designers develop SoCs. These software updates demonstrate the multifaceted values of IC designers at various stages of the design process. Still, some characteristics of a strong EDA tool remain the same. 

For instance, the usability of software can be a major deciding factor; if an engineer encounters a steep learning curve to learn a platform, this can significantly impede the design process. At the end of the day, while these software tools help improve design, reliability, and time to market, what really matters is the design engineer’s preferences and needs for a specific project.

Source: All About Circuits