In previous articles, we’ve taken a look at the original JTAG standard, IEEE 1149.1. This included the JTAG test access port (TAP), which allows the user to manipulate a state machine to access device internals and to run boundary-scan tests.
But while this information is essential for understanding JTAG, it is also necessary to understand the physical side, including the connectors and pinouts, and the commercial JTAG interfaces available on the market. In this article, we’re going to remedy the situation, taking a less theoretical approach to JTAG as a whole.
JTAG Connectors
There is no standard connector for JTAG. More often than not, the “JTAG connector” is a standard male header, such as a 0.1” header or a finer pitch header. As we have seen, there are only four (or five) pins required to operate a JTAG TAP. However, a device which is used to ‘communicate’ with the TAP—called a JTAG interface—also needs power and ground connections, and designers can include other connections on the JTAG header if they desire.
So, given a board, how should a designer provide JTAG access? And, given a new board, where should you look to find the JTAG connector?
Although there is no one standard header for JTAG interfaces, several header types have become more or less standardized among manufacturers. These include the ARM JTAG 20, the ARM JTAG 14, the TI JTAG 14, the STDC14 from STMicroelectronics, the OCDS 16-pin header [pdf] from Infineon, the CoreSight 10, the CoreSight 20, the MIPI 34, and the Mictor 38. Segger defines their J-Link and J-Trace connectors to be nearly identical to the ARM JTAG 20.
Most headers are shrouded or unshrouded male headers, with 10, 14, or 20 pins, and 0.1” or 0.05” pin pitch. Examples are shown in Figure 1.
Figure 1. Common headers used for connecting to JTAG interfaces.
The pinouts for various JTAG interfaces (linked above) are shown in Figure 2. Here you’ll find the standard pins for JTAG (TDI, TDO, TCK, TMS, nTRST), as well as serial wire debug (SWDIO, SWCLK, SWO), and additional functions for debugging, like core tracing.
Figure 2. Pinouts of various JTAG interfaces, shown on 0.1” shrouded male headers in this case.
Particularly notable among the added pins are nSRST (full system reset), which forces the target to fully reset, and VTREF (voltage target reference), connected to the target supply rail for JTAG interface hardware level-shifting.
JTAG Interfaces
Several JTAG interfaces (also called JTAG debug probes) are available on the market. In the open-source hardware arena, there is the Black Magic Probe or BMP, developed by 1BitSquared and Black Sphere Technologies, used as an ARM JTAG interface, which has a large and active community supporting it. Black Magic Probe can also refer to any JTAG interface which has had its firmware replaced with the Black Magic Probe firmware.
The commercial, widely used debug probes from Segger include the J-Link (shown in Figure 3) and the J-Trace, a considerably more advanced and capable debug probe suitable for industrial applications. Where the J-Link can be found for under $100 under an education license, or for between $400 – $1,000 for commercial applications, the J-Trace costs between $1,700 and $2,500.
Figure 3. Segger J-Link PRO debugging probe and JTAG interface
Specific vendors will also sell JTAG interfaces for their products. STMicroelectronics provides the STLINK series (including the STLINK/V2, and the STLINK-V3SET) for their STM8 and STM32 products, Atmel (now Microchip) provides the Atmel-ICE, NXP has the S32 Debug Probe—the list goes on.
FPGAs also use JTAG to download bit streams onto devices/memories, but these interfaces are more often called download cables. Examples include Xilinx’s Platform Cable II and Altera’s FPGA download cable, formerly known as the USB-Blaster II, now rebranded as the Intel FPGA Download Cable II.
So what exactly is going on in these devices that makes them so expensive? What functions do they support, and how does a designer use them? Generally, if you look inside a low-end debug probe, you’ll find the following:
- A microcontroller as the main JTAG controller
- A USB interface, which may be embedded in the microcontroller or may come separately in, for example, an FTDI chip
- Level shifting circuitry for logic compatibility
- Switching circuitry for enabling and disabling different paths, pull-ups, etc.
And that’s about it. As an example, look at the Black Magic Probe hardware files, available on Github. Much of the work (and cost) comes on the software end, providing powerful (sometimes real-time) debugging tools that allow a developer to make the most of the Arm CoreSight architecture.
Conclusion
To this point, we have covered the JTAG standard, including the test access port (TAP) and its state machine. In this article, we took a look at the physical side of JTAG, investigating the connectors and interfaces available to the designer from the open-source up to the commercial high-end.
From here, all that remains is a closer look at the Arm CoreSight architecture and its debug interface (ADI), which will include the increasingly common serial wire debug (SWD) JTAG alternative.
