While gallium nitride (GaN) was once confined to the research realm, in 2021, GaN-based transistors are readily established as a mainstay power component. In fact, IMS Research forecasts that the GaN semiconductor market will exceed $1 billion in 2021.

The primary reason that GaN is at an all-time high in popularity? Performance. Compared to silicon FETs, GaN offers extremely high electron mobility, meaning smaller on-resistances and significantly faster switching speeds than silicon-based transistors.

Comparison of a 48 V to 12 V buck converter with GaN

Comparison of a 48 V to 12 V buck converter with GaN in the optimal layout against a 100 V Si MOSFET. Image used courtesy of EPC

Yet, designers cannot simply take out a silicon FET, plop in a GaN FET, and expect to reap the benefits of GaN. Driving the two devices does differ, and to truly unlock GaN’s potential an engineer must learn the necessary techniques. To gain more insight about how to design with GaN, we sat down with Alex Lidow, CEO of Efficient Power Conversion (EPC).

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Revisiting PCB Basics—But for GaN

“Up until now, when you designed a power circuit, the power transistors were the dominating characteristic,” Lidow remarks. “Its resistance, inductance, and capacitance were all dominating characteristics. But with GaN, we’ve changed all of those by an order of magnitude or more.”

The result of this order of magnitude change has been an entirely new focus in the design of power circuits on the PCB level. Interestingly, in a GaN circuit, the dominating characteristics are actually the PCB itself, focusing on the layout and the associated parasitics.

Design Tip #1: Check Your Parasitics

Lidow’s first design tip for switching to GaN-based transistors is to be aware of parasitics, particularly the parasitic inductances. “The primary delay we see out there is that people make layouts that have a lot of parasitics in them that gives them unintended noise and ringing,” he explains.

Now that the MOSFETs are no longer the dominant source of parasitics, greater attention and understanding of PCB parasitics is necessary. Parasitic inductance and capacitance are unavoidable in design, but can certainly be mitigated.

In a reference PCB design provided by EPC, the company illustrates how to minimize parasitic inductances by creating the smallest power loop and gate loop possible. This can be achieved by utilizing the inner PCB layer to form the optimal return path.

EPC reference layout

EPC reference layout. Image used courtesy of EPC

The effects of parasitic capacitance and inductance can be also minimized with proper layout and shielding. Unintentional crosstalk and coupling can be mitigated by routing sensitive traces between ground and power planes, for example.

Design Tip #2: Watch Out for Magnetics

When working with a higher-frequency design, a dominating characteristic then becomes the magnetic fields associated with the PCB. In high-speed switching converters like the buck converter or an LLC converter, this can significantly impact performance by introducing unwanted effects such as ringing.

Here, Lidow offers tip number 2: “Pay more attention to the kinds of magnetics that you use,” he advises. He also notes that designers should be aware of “the interaction of your choice of magnetics with your choice of topology, your choice of frequencies, and your choice of controllers.”

Solid reference plane

One of the most effective ways to address EMI and crosstalk is to design a solid reference plane, according to Signal Consulting. Image used courtesy of Dr. Howard Johnson and Signal Consulting, Inc.

EPC suggests that when working with multilayer PCBs, designers might want to create a low-profile, magnetic field self-canceling loop to lower the effects of magnetics. Layout is key here, where you can leverage the fact that a current of a specific direction on a PCB will have an equal and opposite current returning to its source through the power and ground system. Opposite currents will create canceling magnetic fields. With multiple small magnetic field-canceling loops formed, the total magnetic energy—and therefore inductance—is significantly reduced.

Design Tip #3: Brush Up on Digital Control

With GaN, particularly DC-DC conversion, it’s all about digital control, Lidow explains. GaN solutions paired with digital control can boost efficiency while shrinking board space and system costs—especially for high-density computing applications like gaming.

Research has shown that GaN-based converters tend to be more sensitive to dead-time related loss due to GaN’s faster-switching transition and high reverse voltage drop. As a result, it’s been shown that improper selection of dead-time value can offset its advantage over silicon solutions. Digital control often allows for greater high-time resolution and optimal dead-time management for GaN.

Multi-loop 2-phase converter control block diagram

Example of a multi-loop 2-phase converter control block diagram, used in this case to regulate both inductors to the same value. Image used courtesy of EPC

Digital control also enables the use of GaN-compatible gate drivers. These drivers tend to have high drive strength, allowing for fast switching and high-side gate voltage clamping for gate overvoltage protection.

New GaN Integrations to Come

What does GaN’s trajectory for 2021 look like? Lidow points to additional integration. “We’ll see GaN implemented things that require higher speed and low cost first,” Lidow comments. The company expects to see technologies such as time-of-flight systems, DC-DC conversion, motor drives, and radiation-hardened ICs coming out with GaN implementations within the year.

What surprised you about working with GaN FETs? Any tips for your fellow designers? Share your ideas in the comments below.

This post was first published on: All About Circuits

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