When discussing MOS transistors, there are basically six types of leakage current components in short channel devices:
- Reverse bias pn junction leakage current
- Subthreshold leakage current
- Drain-induced barrier lowering
- Vth roll off
- Effect of operating temperature
- Tunneling into and through gate oxide leakage current
- Leakage current due to hot carrier injection from the substrate to gate oixide
- Leakage current due to gate-induced drain lowering (GIDL)
Before continuing, be sure you’re familiar with the basic concepts of MOS transistors.
1. Reverse Bias pn Junction Leakage Current
The drain/source and substrate junctions in a MOS transistor are reverse biased during transistor operation. This results in reverse-biased leakage current in the device. This leakage current can be due to drift/ diffusion of minority carriers in the reverse-biased region and electron-hole pair generation due to the avalanche effect. The pn junction reverse-biased leakage current depends on doping concentration and junction area.
For heavily doped pn junction of drain/source and substrate regions, band-to-band tunneling (BTBT) effect dominates the reverse bias leakage current. In band-to-band tunneling, electrons tunnel directly from the valence band of the p region to the conduction band of n region. BTBT is visible for electric fields greater than 106 V/cm.
Figure 1. Band-to-band tunneling in reverse-biased pn junction of a MOS transistor. All images used courtesy of K.Roy, et al., “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits”; Proc. of IEEE, Vol. 91, No. 2, Feb 2003.
In the context of this article, tunneling phenomena takes place even when the energy of the electron is much lesser than the potential barrier.
2. Subthreshold Leakage Current
When the gate voltage is less than the threshold voltage Vth but greater than zero, the transistor is said to be biased in the subthreshold or weak inversion region. In weak inversion, the concentration of minority carriers is small but not zero. In such a case, for typical values of |VDS| > 0.1V, the entire voltage drop takes place across the drain-substrate pn junction.
The electric field component between the drain and source, parallel to the Si-SiO2 interface is small. Due to this negligible electric field, the drift current is negligible and the sub-threshold current mainly consists of diffusion current.
Drain-Induced Barrier Lowering
Subthreshold leakage current is mainly due to drain-induced barrier lowering or DIBL. In short channel devices, the depletion region of drain and source interact with each other and reduce the potential barrier at the source. The source is then able to inject charge carriers into the surface of the channel resulting in sub-threshold leakage current. DIBL is pronounced in high drain voltages and short channel devices.
Vth Roll Off
The threshold voltage of MOS devices reduces due to channel length reduction. This phenomenon is called Vth Roll-Off. In short channel devices, the drain and source depletion region enter further into the channel length, depleting a part of the channel.
Due to this, lesser gate voltage is required to invert the channel reducing the threshold voltage. The phenomena is pronounced for higher drain voltages. The reduction in threshold voltages increases the sub-threshold leakage current – as the sub-threshold current is inversely proportional to the threshold voltage.
Effect of Operating Temperature
Temperature also plays a part in leakage current. Threshold voltage decrease with increasing temperature. Or in other words, sub-threshold current increases with increasing temperature.
3. Tunneling into and Through Gate Oxide Leakage Current
In short channel devices, thin gate oxide results in high electric fields across the SiO2 layer. The low oxide thickness with high electric fields result in electrons tunneling from the substrate to gate and from gate to the substrate through the gate oxide – resulting in gate oxide tunneling current.
Figure 2. Energy band diagrams of MOS transistors with (a) flat band, (b) a positive gate voltage, and (c) a negative gate voltage
Consider the energy band diagrams as shown. The first diagram is of a flat band MOS transistor – when there is no charge present in it. When the gate terminal is positively biased, the energy band diagram changes as shown in the second diagram. The electrons at the strongly inverted surface tunnel into or through the SiO2 layer giving rise to gate current. On the contrary, when a negative gate voltage is applied, electrons from the n+ polysilicon gate tunnel into or through the SiO2 layer giving rise to gate current.
There are primarily two types of tunneling mechanisms between the gate and the substrate. They are (a) Fowler-Nordheim tunneling where the electron tunnel through a triangular potential barrier and (b) Direct tunneling where the electron tunnel through a trapezoidal potential barrier.
Figure 3. Energy band diagrams showing (a) Fowler-Nordheim tunneling through triangular potential barrier of the oxide and (b) Direct tunneling through trapezoidal potential barrier of the oxide
4. Leakage Current Due to Hot Carrier Injection from the Substrate to Gate Oxide
In short channel devices, the high electric field near the substrate-oxide interface energizes the electrons or holes and they cross the substrate-oxide interface to enter the oxide layer. This phenomenon is known as hot carrier injection.
Figure 4. Energy band diagram depicting electrons gaining sufficient energy due to high electric field and crossing over the oxide barrier potential (hot carrier injection effect)
This phenomenon is more likely to affect electrons than holes. This is because electrons have a lesser effective mass and a lesser barrier height as compared to holes.
5. Leakage Current Due to Gate-Induced Drain Lowering (GIDL)
Consider an NMOS transistor with a p-type substrate. When there is a negative voltage at the gate terminal, positive charges accumulate just at the oxide-substrate interface. Due to the accumulated holes at the substrate, the surface behaves as a p-region more heavily doped than the substrate. This results in a thinner depletion region at the surface, along the drain-substrate interface (when compared to the thickness of the depletion region in the bulk).
Figure 5. (a) Formation of thin depletion region at the drain-substrate interface along the surface and (b) flow of GIDL current due to carriers generated by avalanche effect and BTBT
Due to thin depletion region and higher electric fields, avalanche effect and band-to-band tunneling (as discussed in the first section of this article) take place. Thus, minority carriers in the drain region, underneath the gate are generated and are pushed into the substrate by the negative gate voltage. This adds to the leakage current.
6. Leakage Current Due to Punch-Through Effect
In short channel devices, due to the proximity of drain and source terminals, the depletion region of both the terminals come together and eventually merge. In such a condition, Punch Through is said to have taken place.
The punch-through effect lowers the potential barrier for the majority carriers from the source. This increases the number of carriers entering into the substrate. Some of these carriers are collected by the drain and the rest contribute to leakage current.
You should now be familiar with six types of leakage current associated with MOS transistors. If you have additional questions about these concepts, please leave a comment below.
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