Innovation in computing is an ongoing trend that keeps growing exponentially in today’s digital world. With data transfer being a major requirement in computing, we will discuss the PCIe (peripheral computer interconnect express) bus in this article.
Growing computing power has raised a requirement for the transfer of progressively larger amounts of data between memory, peripherals, and the CPU for processing. Such data transfers are managed by the computer bus connecting devices to the PC memory that in turn impacts the speed of computing tasks. To address the growing requirement for bandwidth, the PCI Express bus was introduced by Intel in 2004, superseding the slower PCI (peripheral computer interconnect) bus.
In this article, we will cover:
What are PCI connections?
PCI is a popular connection interface used for attaching computer peripherals such as RAM, ethernet, and network cards, I/O cards to a motherboard. It was introduced in 1992 with the aim of supporting complex data transfers and evolved its purpose way beyond the same. The PCI bus was made to be available in 32-bit and 64-bit versions. The PCI technology has undergone various updates to evolve into PCI Express which is still under development.
How PCI Express works
PCI Express is a serial connection that works more as a network than as a bus. Instead of one bus handling data from various sources, it includes a switch controlling various point-to-point serial connections. Such connections will spread outward from the switch leading to the devices where the data is required to go. As each device has its own dedicated connection, devices no longer share bandwidth as they do on a conventional bus.
Also read about the challenges of microelectronics designs and their benefits.
Evolution of PCI
The PCI specification was utilized by the computer industry from 1992 to 2004 as the primary local bus system within a computer. It standardized how PCI expansion cards ranging from a network card to a modem can be self-installed and exchange information with the CPU. CPU processor frequencies rose from 66MHz in 1993 to well over 3GHz in 2003. The existing PCI bandwidth had trouble keeping up with the I/O processing capabilities of the new processors which is what led to the development of PCI Express spec.
From 2004 Intel introduced its PCI express spec which kept the core of PCI’s software infrastructure and wholly replaced the hardware infrastructure that could handle higher I/O requirements of processors. PCI had parallel interconnect whereas the new PCI Express has a serial point-to-point interconnect capable of high bandwidth transfers.
The different PCIe versions
PCIe currently comes in four different generations: PCIe 1.0, PCIe 2.0, PCIe 3.0 and PCIe 4.0. The bandwidth doubles with each generation. Given below are the detailed specifications of the PCIe generations.
|PCI express version||Transfer rate (GigaTransfers per second)||x1 Throughput||x4 Throughput||x8 Throughput||x16 Throughput|
|1.0||2.5 GT/s||250 MB/s||1.0 GB/s||2.0 GB/s||4.0 GB/s|
|2.0||5 GT/s||500 MB/s||2.0 GB/s||4.0 GB/s||8.0 GB/s|
|3.0||8 GT/s||984.6 MB/s||3.94 GB/s||7.88 GB/s||15.8 GB/s|
|4.0||16 GT/s||1969 MB/s||7.88 GB/s||15.75 GB/s||31.5 GB/s|
What does PCI Express 3.0 x16 mean?
From the table given above, you can see that it is a thirst generation PCI Express with a throughput of 15.8GB/s. The number 16 refers to the number of lanes in a PCIe card and is called “by 16”. A lane is made of two differential signaling pairs with one pair used to receive data and another used to transmit data. Each lane is utilized as a full-duplex byte stream, sending and receiving data in 8-bit format simultaneously in both directions between the endpoints of a link. This means each lane is made of four signal traces or wires. Lane count is written with an “x” prefix, and x16 is the largest size that is commonly used.
You can also learn more about DDR memory and the challenges in PCB design.
What is the difference between SATA, PCIe, and NVMe?
PCIe is a standard connection for internal devices in a computer and has been around for several years and is seeing increasing adoption due to its speed.
NVMe (non-volatile memory express) is an interface protocol that has been constructed especially for solid-state drives (SSDs). NVMe works with PCIe to transfer data between SSDs. This enables rapid storage in SSDs and is an enhancement over older hard disk drive (HDD) interfaces such as SATA and SAS.
SATA (serial advanced technology attachment), is a successor to the Parallel ATA bus interface used to connect SSDs, hard disk drives (HDDs), and optical drives. Ever since SATA was introduced in 2000 and has been updated a number of times to enhance the ability to transfer data. SATA I (1.0) has data transfer rates of about 150MB/s and the latest SATA III can achieve speeds of up to 600MB/s.
PCI Express layout and routing guidelines
Given are some PCI Express layout and routing guidelines that enable efficient design.
Trace routing specifications
When compared to most high-speed devices available, PCIe generations permit longer trace in their layout routing specs. Every generation comes with its own specifications on impedance and maximum trace lengths for varying data transfer rates. These should be closely followed to obtain the required performance. The exact routing specifications will depend on which PCIe generation you are utilizing for your design.
Also, read an article on Learning about High-Speed PCB Design
Trace lengths in Gen 1 and Gen 2 both let RX (received) and TX (transmitted) signal traces reach up to 21 inches in length. When it comes to Gen 3, trace lengths can only go up to 14 inches on signal trace PCIe planes. While each TX trace pair can have only two vias, RX pairs can include up to four vias to maintain impedance within the required specification. A COM Express carrier board allows for trace lengths of up to 9 inches for Gen 1 and 2 when the traces are being sent to a PCIe slot.
The differential impedance of signal lines depends on the bus used to connect to the PCIe board.
|Type of PCB||Differential Impedance (Ohms)|
|PCI-SIG bus Gen 1||85|
|PCI-SIG bus Gen 2||85|
|PCI-SIG bus Gen 3||85|
|COMCDG Rev. 1.0 bus Gen 1 PCIe||92|
|COMCDG Rev. 1.0 bus Gen 2 PCIe||92|
|COMCDG Rev. 2.0 bus Gen 3 PCIe||85|
The tolerance for differential impedance values also differs among the various PCIe generations and bus standards. The values may be different for each bus and generation combination, but they can be found in the COMCDG Rev. 2.0 specification.
When keeping the impedance of microstrip traces within specified tolerances, you need to use PCB design software to include controlled impedance routing features. The interactive routing tool in the software will ensure your traces are spread out with the right spacing and geometry.
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Stack-up and grounding
Standard PCIe boards incorporate a 4-layer stack-up with two interior power planes and two signal layers on each surface. Each power layer can be brought to varying bias levels based on device requirements. Other designs for PCIe boards go for a 6-layer stack-up with two signal layers that run between two power layers. In another scenario, one of the power planes can be replaced with a ground plane. In both cases, you can achieve better immunity to EMI by routing signal traces on the inner layers.
You can even route traces with varying data rates on different layers. For instance, in a mixed-signal board such as the ones in a WiFi device on a PCIe card, you can route digital traces on the outer layers and the RF traces on the inner layers. The ground/power planes will effectively block noise from reaching the sensitive analog signal traces.
Regardless of the stack-up used, you will need to meet the overall board thickness standard of 1.57 mm or 1 mm for PCIe Mini. You will also need to consider standard high-speed design techniques as the Gen 1 of PCIe operates at 2.5 GHz clock speed with future generations increasing in speed.
PCIe differential pair routing
Routing around obstructions and component placement and via placement on a PCIe board is really important. There needs symmetric routing to pins, pads, and components along with the BGA breakout routing. Differential pairs need to be tightly coupled throughout their entire length, with variations in one trace due to vias, pads, or components being mirrored in the other trace. This ensures crosstalk is minimized throughout the differential pair length. Similar practices need to be applied while routing BGA breakouts or breakouts from other components.
Also see How to Avoid crosstalk in HDI substrate.
As the performance requirements of high-speed PCB design continue to increase, it becomes critical to ensure that your design meets PCIe layout routing specifications. PCB manufacture for PCIe requires a great deal of expertise and experience that only a few manufacturers can provide. So choose wisely!
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