We conclude our series by discussing a proposed model for ADC simulation.

You can catch up the conversation with the following links:

Please recall that a complete list of abbreviations, glossaries, and a complete list of references can be found in the first article of the series.

A Proposal for an Even Better ADC Model

A two-tone test signal gives more information about ADC performance than a one-tone. Your author’s model gives a good match to the manufacturer’s model for a particular ADC so bit error rate simulations could be run conveniently. This ADC happened to have a very wide input bandwidth.

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For ADC with lower bandwidths, the addition of a low-pass filter as shown in Figure 1 would give a better model.

adding a low pass filter to an adc model and dac modeling hyperedge embed image

Figure 1. An improved ADC model based on the previous article

Also, as discussed in the first section of our previous article, an improved model would allow up to 6 dB of additive white Gaussian noise to be added, to give a better match to the real ADC’s noise floor.

The manufacturer’s model was a “behavioral”, not an exact model. It would be good to do the same comparison against a detailed SPICE model, or measurements on an actual physical device.

Models for Digital-to-Analog Converters (DACs)

References [19] through [26] present some sort of DAC model, whilst [27] through [29] describe characteristics of DACs, but not models. Of those presenting models most ([19], [20], [22], and [23]) present models that seem of interest to DAC designers, not users, giving detailed specific models to determine things like SNR, or the effect of clock jitter on the output spectrum.

Others present models which seem too simple. These are [25], which only takes into account clipping without quantization; and [26], which models quantization and clipping as additive processes, which is only valid for Gaussian inputs.

Reference [21] models the DAC output (y(t)) as a function of the DAC input (x(t)), using the equation:

y(t) = x(t) + yHQ(x(t))  +  yCM(x(t))  + yVQ(x(t))

Equation 1

where these are the corresponding terms: 

  • yHQ(x(t)) accounts for “horizontal quantization” (ideal time sampling)
  • yCM(x(t)) accounts for “clock source modulation” (clock jitter)
  • yVQ(x(t)) accounts for “vertical quantization” (amplitude quantization) including integral non-linearity. 

The expressions for these terms are not extremely complicated, so this might make a good model for simulation of DACs. The input, x(t), can be from a floating-point implementation of the modulation algorithm, or from a fixed point one with output M bits, where M > NE; where NE is the number of effective bits of the DAC.

Reference [24] presents a model which takes into account differential non-linearity (DNL), integral non-linearity (INL), gain and offset errors, glitch impulse area, and settling time.

Figure 5 of [24] shows a block diagram of the model. It consists of additive random errors to model DNL; additions of deterministic functions of time to model glitches; a polynomial function to model INL, gain and offset errors; a delay and time slew (which is not explained in the text); a low-pass filter to model settling time; and a noise model (also not explained in the text). Figure 5 from [24] could be modified some, producing Figure 2 here, which is the inverse of the ADC model in Figure 1; with the addition of additive noise available if the output noise due to the quantization is not enough.

adding a low pass filter to an adc model and dac modeling 1 hyperedge embed image

Figure 2. A modification of a DAC model from Naoues, M.; Morche, D.; Dehos, C.; Barrak, R.; and Ghazel, A, [24]

The reader might wonder why, since the input to the DAC is already digital, the sampler and quantizer in Figure 2 are needed.

Often, for simulation, a continuous-time, floating point, algorithm is available; and it is not worth the expense to convert it to a clocked, fixed-point version. (Continuous-time means the simulation sampling frequency is high enough so there are no sampling effects.) Also, often the actual number of bits available on the DAC interface (the advertised number of bits) is greater than the ENOB.


What additional questions do you have about modeling ADCs (and DACs) for system simulation? Share your thoughts in the comments below.

References

DAC Analysis, Models, Simulation, Testing, and Specifications

[19] Wikner, J.J.; Nianxiang Tan, “Modeling of CMOS digital-to-analog converters for telecommunication,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol.46, no.5, pp.489,499, May 1999

[20] Angrisani, L.; D’Arco, M., “Modeling Timing Jitter Effects in Digital-to-Analog Converters,” Instrumentation and Measurement, IEEE Transactions on, vol.58, no.2, pp.330,336, Feb. 2009

[21] D’Apuzzo, M.; D’Arco, M.; Liccardo, A; Vadursi, M., “Modeling DAC Output Waveforms,” Instrumentation and Measurement, IEEE Transactions on, vol.59, no.11, pp.2854,2862, Nov. 2010

[22] Myderrizi, I; Zeki, A, “Current-Steering Digital-to-Analog Converters: Functional Specifications, Design Basics, and Behavioral Modeling,” Antennas and Propagation Magazine, IEEE, vol.52, no.4, pp.197,208, Aug. 2010

[23] Sang Min Lee; Taleie, S.M.; Saripalli, G.R.; Dongwon Seo, “Clock-Phase-Noise-Induced TX Leakage Estimation of a Baseband Wireless Transmitter DAC,” Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.59, no.5, pp.277,281, May 2012

[24] Naoues, M.; Morche, D.; Dehos, C.; Barrak, R.; Ghazel, A, “Novel behavioral DAC modeling technique for WirelessHD system specification,” Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on, vol., no., pp.543,546, 13-16 Dec. 2009

[25] Kitaek Bae; Changyong Shin; Powers, E.J., “Performance Analysis of OFDM Systems with Selected Mapping in the Presence of Nonlinearity,” Wireless Communications, IEEE Transactions on , vol.12, no.5, pp.2314,2322, May 2013

[26] Ling, W.A, “Shaping Quantization Noise and Clipping Distortion in Direct-Detection Discrete Multitone,” Lightwave Technology, Journal of, vol.32, no.9, pp.1750,1758, May1, 2014

[27] Engel, G.; Fague, D.E.; Toledano, A, “RF digital-to-analog converters enable direct synthesis of communications signals,” Communications Magazine, IEEE, vol.50, no.10, pp.108,116, October 2012

[28] Pearson, Chris; “High Speed, Digital to Analog Converters Basics”; Texas Instruments Application Report SLAA523A; 2012

[29] Munson, Justin; “Understanding High Speed DAC Testing and Evaluation”; Analog Devices Application Note AN-928; 2013

This post was first published on: All About Circuits

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